Parallel Double Error Correcting Code Design to Mitigate Multi-Bit Upsets in SRAMs. In Proceedings of the 2011 12th International Symposium on Quality Electronic Design, Santa Clara, CA, USA, 14–16 March 2011 pp. BCH Code Based Multiple Bit Error Correction in Finite Field Multiplier Circuits. SEU tolerant memory using error correction code. Error detection in majority logic decoding of euclidean geometry low density parity check (EG-LDPC) codes. Schemes for eliminating transient-width clock overhead from SET-tolerant memory-based systems. Radiation-Induced Fault Simulation of SOI/SOS CMOS LSI’s Using Universal Rad-SPICE MOSFET Model. A highly reliable memory cell design combined with layout-level approach to tolerant single-event upsets. In Proceedings of the 2009 IEEE International Reliability Physics Symposium, Montreal, QC, Canada, 26–30 April 2009 pp. Reliability of High Performance Standard Two-Edge and Radiation Hardened by Design Enclosed Geometry Transistors. The authors declare no conflict of interest. Single Event Upset (SEU) and Radiation-Hardening Design Techniques For a pMOSFET whose drain or source is p+-doped, the node voltage can be unintentionally raised due to SET.

This phenomenon is called single event transient (SET). For example, in off nMOSFET, the source or drain is n+-doped and the electrons are collected towards the n+ side, and the node voltage is substantially lowered. This current results in a sudden voltage change at the source or drain node. Thus, the generated carriers (i.e., electron–hole pairs) are collected by the electric field, which creates a temporal junction current. Along the path of particle injection, the depletion region of the p–n junction is extended, which leads to the generation of a high electric field. If an energetic particle hits a source or drain node and passes through the transistor, electron–hole pairs are generated near the p–n junction of the source or drain diffusion. The voltage change occurs in the following procedure. In integrated circuits, the diffusion nodes (drain or source) of the “off” transistors are sensitive to the voltage change due to the particle impact.

Static random access memory